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1 www.pericom.com pi6c491 1506 reva 06/12/14 pi6c20800b features ? ? 6 lvpecl outputs ? ? up to 1.5ghz output frequency ? ? ultra low additive phase jitter: < 0.03 ps (typ) (diferential 156.25mhz, 12khz to 20mhz integration range) ? ? single diferential input ? ? low delay from input to output (tpd typ. < 700ps) ? ? 2.5v / 3.3v power supply ? ? industrial temperature support ? ? tssop-20 package p i 6 c 49115 0 6 block diagram vbb ref_in+ ref_in- clk0 clk0# clk1 clk1# clk2 clk2# clk5 clk5# clk3 clk3# clk4 clk4# pin confguration (20-pin tssop) description te pi6c4911506 is a high performance fanout bufer device - which supports up to 1.5ghz frequency. tis device is ideal for systems that need to distribute low jitter clock signals to multiple destinations. applications ? ? networking systems including switches and routers ? ? high frequency backplane based computing and telecom platforms 6 output high performance lvpecl fanout buffer 1 2 3 clk1# 4 clk1 5 clk0 6 clk2 7 clk3 8 clk2# vdd clk5# clk4 20 19 18 17 vdd clk0# clk4# clk5 clk3# 9 16 vdd 10 vdd 15 vee ref_in+ 14 vbb 13 ref_in- 12 11 14-0093
2 www.pericom.com pi6c491 1506 reva 06/12/14 pin # pin name ty pe description 1, 8, 13, 20 v dd power power supply 2, 3 clk0#, clk0 output diferential lvpecl output 4, 5 clk1#, clk1 output diferential lvpecl output 6, 7 clk2#, clk2 output diferential lvpecl output 9 ref_in+ input pulldown diferential lvpecl input 10 ref_in- input pull up/ pull - down diferential lvpecl input 11 v bb output bias voltage 12 v ee power negative supply pin 14, 15 clk3#, clk3 output lvpecl output clock 16, 27 clk4#, clk4 output lvpecl output clock 18, 19 clk5#, clk5 output lvpecl output clock pinout table pin characteristics symbol parameter min ty p max units r pullup input pullup resistor 50 k r pulldown input pulldown resistor 75 k p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
3 www.pericom.com pi6c491 1506 reva 06/12/14 maximum ratings (over operating free-air temperature range) ote stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. supply voltage..........................................................4.6v storage temperature .............................................. -65oc to+155oc ambient temperature with power applied ......... -40oc to+85oc 3.3v analog supply voltage ...................................... -0.5 to +3.7v esd protection (hbm) ......................................................... 2000v junction temperature ............................................................ 125oc dc electrical characteristics poer uppl dc characterisitcs (t a = -40oc to 85oc) symbol parameter condition min ty p max units v dd supply voltage 3.0 3.3 3.6 v 2.375 2.5 2.625 i ee power supply current outputs unloaded 71 95 ma i dd power supply current outputs unloaded 72 95 ma lvpecl dc characteristics, (t a = -40oc to 85oc) symbol parameter condition min ty p max units v ih input high voltage v dd = 3.3 v 2.0 2.36 v v dd = 2.5 v 1.275 1.56 v v il input low voltage v dd = 3.3 v 1.43 1.765 v v dd = 2.5 v 0.63 0.965 v i ih input high current ref_in+, ref_in- 150 a i il input low current ref_in+ -10 a ref_in- -150 v pp input peak to peak voltage 150 1200 mv v oh output high voltage v dd = 3.3 v 2.06 2.54 v v dd = 2.5 v 1.43 1.75 v v ol output low voltage v dd = 3.3 v 1.32 1.7 v v dd = 2.5 v 0.82 1.02 v v swing peak to peak output voltage 625 870 mv v bb output voltage reference v dd = 3.3 v 1.76 1.98 v v cmr input common voltage range 1.2 v dd v p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
4 www.pericom.com pi6c491 1506 reva 06/12/14 ecl dc characterisitcs, (t a = -40oc to 85oc) symbol parameter condition min ty p max units v ih input high voltage -1.225 -0.94 v v il input low voltage -1.87 -1.535 v i ih input high current ref_in+, ref_in- 150 a i il input low current ref_in+ -10 a ref_in- -150 v pp input peak to peak voltage 150 1200 mv v oh output high voltage -1.12 -0.89 v v ol output low voltage -1.895 -1.65 v v swing peak to peak output voltage 625 870 mv v bb output voltage reference -1.54 -1.32 v v cmr input common voltage range v ee + 1.2 0 v note: note1: single ended input limited to v ee -3v in lvpecl p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
5 www.pericom.com pi6c491 1506 reva 06/12/14 ac electrical characteristics ac characteristics, (t a = -40oc to 85oc) symbol parameter condition min ty p max units f out output frequency 1.5 ghz t pd propagation delay v dd = 3.3 v 400 520 650 ps v dd = 2.5 v 450 560 700 t sk(0) output skew 50 ps t sk(p) part to part skew 230 ps t jitter additive jitter 0.03 ps t r /t f output rise/ fall time 20% to 80%, freq= 156.25mhz 100 180 250 ps 10% to 90%, freq = 156.25mhz 340 500 800 ps p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
6 www.pericom.com pi6c491 1506 reva 06/12/14 propagation delay and output skew ref_in+ ref_in- t pdn v oh v ol clkn/ clkn# propagation delay t pd output skew t sk(o) clkn+1/ clkn+1# t pdn+1 t sk(o) t pdn+1 t sk(o) t pdn v oh v ol v oh v ol t sk(o) = t pdn+1 - t pdn part to part skew ref_in+ ref_in- t pd1 v oh v ol part1 clk/clk# part-to-part skew t sk(p) part2 clk/clk# t pd2 t sk t pd2 t sk t pd1 v oh v ol v oh v ol t sk(p) = t pd2 - t pd1 t pw clkn/ clkn# duty cycle o dc t period v oh v ol o dc = ( t pw / t period ) x 100% output duty cycle p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
7 www.pericom.com pi6c491 1506 reva 06/12/14 phase noise plots f additive jitter = (output jitter 2 - input jitter 2 ) p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
8 www.pericom.com pi6c491 1506 reva 06/12/14 lvpecl test circuit 100 z = 50 o z = 50 o 150 150 lvpec l buff er v ddox l = 0 ~ 10 in. p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
9 www.pericom.com pi6c491 1506 reva 06/12/14 application information suggest for unused inputs and outputs outputs all unused outputs are suggested to be lef open and not con - nected to any trace. tis can lower the ic power supply power. power decoupling & routing vdd pin decoupling as general design rule, each vdd pin must have a 0.1uf decou - pling capacitor. for better decoupling, 1uf can be used. locat - ing the decoupling capacitor on the component side has better decoupling flter result as shown in fig. 1. fig 1: placement of decoupling caps diferential clock trace routing always route diferential signals symmetrically, make sure there is enough keep-out space to the adjacent trace (>20mil.). in 156.25mhz xo drives ic example, it is better routing diferen - tial trace on component side as the following fig. 2. clock ic device 2 ref_in - ref_in+ 3 4 5 6 vdd gnd keep out board vias vcc gnd 150 150 156.25m xo 0.1uf *100 *100 is optional if ic has gnd fig 2: ic routing for xo drive clock ic device vdd 11 13 10 9 8 12 14 0.1uf 0.1uf gnd gnd vdd vdd decouple cap. on comp. side gnd clock timing is the most important component in pcb design, so its trace routing must be planned and routed as a frst prior - ity in manual routing. some good practices are to use minimum vias (total trace vias count <4), use independent layers with good reference plane and keep other signal traces away from clock traces (>20mil.) etc. p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
10 www.pericom.com pi6c491 1506 reva 06/12/14 lvpecl and lvds input interface lvpecl and lvds dc/ ac input lvpecl and lvds clock input to this ic is connected as shown in the fig. 3. use vbb lvpecl/lvds ac input lvpecl and lvds ac drive to this clock ic requires the use of vbb output to recover the dc bias for the ic input as shown in fig. 4. cml ac-coupled input cml ac-coupled drive requires a connection to vbb. te cml dc drive is not recommended as diferent vendors have difer - ent cml dc voltage level. cml is mostly used in ac coupled drive confguration for data and clock signals. fig 3: lvpecl/ lvds input fig 4: lvpecl/ lvds ac coupled input cmos clock dc drive input lvcmos clock has voltage voh levels such as 3.3v, 2.5v, 1.8v. cmos drive requires a vcm design at the input: vcm= ? (cmos v) as shown in fig. 7. rs =22 ~33ohm typically. fig 5: cmos dc input vcm design device ic + - zo =100 *150 *150 lvpecl drive ref_in+ ref_in - vbb 100 *150 removed for lvds dcorac lvds device ic + - zo =100 *150 *150 lvpecl drive ref_in+ ref_in - vbb *150 removed for lvds 50 50 0.1u 0.01u 0.01u cmos driver 3.3v, 2.5v, 1.8v rs zo ro ref_in+ ref_in - vcc 3.3v 0.1u rup rdn vcm design vcm cmos v rup rdn vcm 3.3v 1k 1k 1.65v 2.5v 1k 610 1.25v 1.8v 1k 380 0.9v diff. input vbb p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
11 www.pericom.com pi6c491 1506 reva 06/12/14 device lvpecl output terminations lvpecl output popular termination te most popular lvpecl termination is 150ohm pull-down bias and 100ohm across at rx side. please consult asic data - sheet if it already has 100ohm or equivalent internal termina - tion. if so, do not connect external 100ohm across as shown in fig. 6. tis popular terminations advantage is that it does not allow any bias through from vcc. tis prevents vcc system noise coupling onto clock trace. lvpecl output tevenin termination fig. 7 shows lvpecl output tevenin termination which is used for shorter trace drive (<5in.), but it takes vcc bias current and vcc noise can get onto clock trace. it also requires more component count. so it is seldom used today. fig. 6 lvpecl output popular termination fig. 7 lvpecl tevenin output termination lvpecl output ac tevenin termination lvpecl ac tevenin terminations require a 150ohm pull- down before the ac coupling capacitor at the source as shown in fig. 8. note that pull-up/down resistor value is swapped compared to fig. 7. tis circuit is good for short trace (<5in.) application only. lvpecl output drive hcsl input using the lvpecl output to drive a hcsl input can be done using a typical lvpecl ac tenvenin termination scheme. use pull-up/down 450/60ohm to generate vcm=0.4v for the hcsl input clock. tis termination is equivalent to 50ohm load as shown in fig. 9. fig. 9 lvpecl output drive hcsl termination fig. 10 lvpecl output ac tenvenin termination p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
12 www.pericom.com pi6c491 1506 reva 06/12/14 lvpecl output v_swing adjustment it is suggested to add another cross 100ohm at tx side to tune the lvpecl output v_swing without changing the optimal 150ohm pull-down bias in fig. 10. tis form of double termina - tion can reduce the v_swing in ? of the original at the rx side. by fne tuning the 100ohm resistor at the tx side with larger values like 150 to 200ohm, one can increase the v_swing by > 1/2 ratio. fig. 10 lvpecl output v_swing adjustment clock jitter defnitions total jitter= rj + dj random jitter (rj) is unpredictable and unbounded timing noise that can ft in a gaussian math distribution in rms. rj test val - ues are directly related with how long or how many test samples are available. deterministic jitter (dj) is timing jitter that is pre - dictable and periodic in fxed interference frequency. total jitter (tj) is the combination of random jitter and deterministic jitter: , where is a factor based on total test sample count. jedec std. specifes digital clock tj in 10k random samples. phase jitter phase noise is short-term random noise attached on the clock carrier and it is a function of the clock ofset from the car - rier, for example dbc/hz@10khz which is phase noise power in 1-hz normalized bandwidth vs. the carrier power @10khz ofset. integration of phase noise in plot over a given frequency band yields rms phase jitter, for example, to specify phase jitter <=1ps at 12k to 20mhz ofset band as sonet standard specif - cation. pcie ref_clk jitter pcie reference clock jitter specifcation requires testing via the pci-sig jitter tool, which is regulated by us pci-sig organiza - tion. te jitter tool has pcie serdes embedded flter to calculate the equivalent jitter that relates to data link eye closure. direct peak-peak jitter or phase jitter test data, normally is higher than jitter measure using pci-sig jitter tool. it has high-frequency jitter and low-frequency jitter spec. limit. for more informa - tion, please refer to the pci-sig website: http://www.pcisig.com/ specifcations/pciexpress/ device thermal calculation fig. 11 shows the jedec thermal model in a 4-layer pcb. fig. 11 jedec ic termal model important factors to infuence device operating temperature are: 1) te power dissipation from the chip (p_chip) is afer subtract - ing power dissipation from external loads. generally it can be the no-load device idd 2) package type and pcb stack-up structure, for example, 1oz 4 layer board. pcb with more layers and are thicker has better heat dissipation 3) chassis air fow and cooling mechanism. more air fow m/s and adding heat sink on device can reduce device fnal die junc - tion temperature tj te individual device thermal calculation formula: tj =ta + pchip x ja tc = tj - pchip x jc ja ___ package thermal resistance from die to the ambient air in c/w unit; tis data is provided in jedec model simulation. an air fow of 1m/s will reduce ja (still air) by 20~30% jc ___ package thermal resistance from die to the package case in c/w unit tj ___ die junction temperature in c (industry limit <125c max.) ta ___ ambiant air temprature in c tc ___ package case temperature in c pchip___ ic actually consumes power through iee/gnd cur - rent p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
13 www.pericom.com pi6c491 1506 reva 06/12/14 termal calculation example to calculate tj and tc of pi6cv304 in an soic-8 package: step 1: go to pericom web to fnd ja=157 c/w, jc=42 c/w http://www.pericom.com/support/packaging/packaging-me - chanicals-and-thermal-characteristics/ step 2: go to device datasheet to fnd idd=40ma max. step 3: p_total= 3.3vx40ma=0.132w step 4: if ta=85c tj= 85 + ja xp_total= 85+25.9 = 105.7c tc= tj + jc xp_total= 105.7- 5.54 = 100.1c note: te above calculation is directly using idd current without sub - tracting the load power, so it is a conservative estimation. for more precise thermal calculation, use p_unload or p_chip from device iee or gnd current to calculate tj, especially for lvpecl bufer ics that have a 150ohm pull-down and equivalent 100ohm diferential rx load. thermal information symbol description condition q ja junction-to-ambient thermal resistance still air 84.0 o c/w q jc junction-to-case thermal resistance 17.0 o c/w p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093
14 www.pericom.com pi6c491 1506 reva 06/12/14 ordering information ordering code packaging type package description operating temperature PI6C4911506LIE l pb-free & green, 20-pin tssop industrial notes: ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com packaging mechanical: 20-contact tssop (l) date: 05/03/12 description: 20-pin, 173mil wide tssop package code: l document control #: pd-1311 revision: f notes: 1. refer jedec mo-153f/ac 2. controlling dimensions in millimeters 3. package outline exclusive of mold flash and metal burr 12-0373 p i 6 c 49115 0 6 6 output high performance lvpecl fanout bufer 14-0093

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